 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice. july 2015 doc id026749 rev 2 1/64 vs6663cb 1.3 megapixel camera module datasheet - preliminary data features ? 1280 x 960 1.3 mpixel resolution sensor ? compact size: 6.5 mm x 6.5 mm x 4.24 mm ? very short focus distance: 16mm ? mipi csi-2 (a) (d-phy v1.0) and ccp2 video data interface ? ultra low power standby mode (<15uw) ? binning 2x2 mode ? defect correction ? 4-channel lens shading correction description the vs6663cb is a compact camera module designed for machine vision applications which require a very sh ort focus distance. it is designed to be used for high quality still camera function and also supports video modes. the camera silicon device is capable of generating raw bayer 1.3 mpixel images up to 30 fps. the vs6663cb supports the cci control and ccp2 and csi-2 data interfaces. the module design is optimized for both footprint and height. a separate hardware accelerator can be incorporated in the phone system to run the algorithms in hardware. th e specification of these devices are contained in a separate document. a. copyright ? 2005 mipi alliance, inc. standard for camera serial interface 2 (csi-2) version 1.01, limited to 1 gbps per lane table 1. device summary order code package packing VS6663CBQ05I/1 smia65 tape and reel www.st.com
contents vs6663cb 2/64 doc id026749 rev 2 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 vs6663cb use in system with hardware coprocessor . . . . . . . . . . . . . . . . 8 1.2 vs6663cb use in a system with software image processing . . . . . . . . . . 9 1.3 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.1 clock input type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.2 pll and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 internal power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.4 power-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.5 hardware standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.6 software standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.7 streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.8 dark calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 camera control interface (cci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 general status registers [0x0000 to 0x001f] . . . . . . . . . . . . . . . . . . . . . 23 4.2.2 frame format description registers [0x0 040 to 0x007f] . . . . . . . . . . . . 24 4.2.3 analog gain description registers [0x008 0 to 0x0093] . . . . . . . . . . . . . . 24 4.2.4 data format description registers [0x00c0 to 0x00c7] . . . . . . . . . . . . . 25 4.2.5 setup registers [0x0100 to 0x01ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.6 integration time and gain registers [0x0 200 to 0x02ff] . . . . . . . . . . . . 27 4.2.7 video timing registers [0x0300 to 0x03ff] . . . . . . . . . . . . . . . . . . . . . . 28 4.2.8 image compression registers [0x0500 to 0x0501] . . . . . . . . . . . . . . . . . 29 4.2.9 test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.10 binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . 30 doc id026749 rev 2 3/64 vs6663cb contents 4 4.2.11 integration time and gain paramete r limit registers [0x1000 to 0x10ff] 31 4.2.12 video timing parameter limit registers [0x1100 to 0x11ff] . . . . . . . . . . 32 4.2.13 binning capability registers [0x1700 to 0x1713] . . . . . . . . . . . . . . . . . . 35 5 video data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1 output size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1.1 analog crop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1.2 binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.3 output crop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2 video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2.1 pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2.2 framerate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2.3 bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 exposure and gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3.1 gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3.2 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3.3 integration and gain parameter retiming . . . . . . . . . . . . . . . . . . . . . . . . 46 7 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.3 power supply - vdig, vana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.3.1 peak current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.4 system clock - extclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.5 power down control - xshutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.6 cci interface - sda, scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.6.1 cci interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.6.2 cci interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.7 ccp2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.7.1 ccp2 interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.7.2 ccp2 interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.8 csi-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.8.1 csi-2 interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 contents vs6663cb 4/64 doc id026749 rev 2 7.8.2 csi-2 interface - ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8 optical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1 lens characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.2 user precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9 on-chip image optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.1 mapped couplet correction (bruce filter) . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2 median filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3 lens shading correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10 mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.1 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 doc id026749 rev 2 5/64 vs6663cb list of tables 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. system input clock frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 table 6. power-up sequence timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. power-down sequence timing constraints for csi2 communications . . . . . . . . . . . . . . . . . 18 table 8. por cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. general status registers [0x0000 to 0x001f] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. frame format description registers [0x0040 to 0x00 7f] . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. analog gain description [0x0080 to 0x0093] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. data format description registers [0x00c0 to 0x00c7 ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. setup registers [0x0100 to 0x01ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. integration time and gain registers [0x0200 to 0x02 ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16. video timing registers [0x0300 to 0x03ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. image compression registers [0x0500 to 0x0501] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18. test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 20. integration time and gain parameter limit registers [0x1000 to 0x10ff]. . . . . . . . . . . . . . . 31 table 21. video timing parameter limit registers [0x1100 to 0x11ff]. . . . . . . . . . . . . . . . . . . . . . . . . 32 table 22. binning capability regi sters [0x1700 to 0x1713] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 23. binning register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 24. external clock frequency examples - 1.3 mpixel resolution raw10 30 fps . . . . . . . . . . . . . 43 table 25. analog gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 26. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 28. power supplies vdig, vana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 29. system clock - extck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 30. power down control - xshutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 31. cci interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 32. cci interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 33. ccp2 interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 34. ccp2 interface - timing characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 35. csi-2 interface - high speed mode - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 36. csi-2 interface - low power mode - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 37. csi-2 interface - high speed mode - ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 38. csi-2 interface - low power mode - ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 39. lens design characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 40. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 list of figures vs6663cb 6/64 doc id026749 rev 2 list of figures figure 1. vs6663cb camera module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. vs6663cb in system with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. vs6663cb in a system with software image processi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. vs6663cb module pinout (viewed from bottom of camera module) . . . . . . . . . . . . . . . . . 11 figure 5. clock input types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. system state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. vs6663cb power-up sequence for ccp2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. vs6663cb power-up sequence for csi-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. vs6663cb power-down sequence for csi-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. por timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. vs6663cb ccp2 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. vs6663cb csi-2 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 14. analog crop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 15. output size within a ccp2 data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 16. clock relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 17. bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 18. analog gain register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 19. cci ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 20. sublvds ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 21. lens shading images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 22. vs6663cb outline drawing - 1 of 3 - all dimensions in mm . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 23. vs6663cb outline drawing - 2 of 3 - all dimensions in mm . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 24. vs6663cb outline drawing - 3 of 3 - all dimensions in mm . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 25. mobile camera applicat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 doc id026749 rev 2 7/64 vs6663cb overview 47 1 overview the vs6663cb 1.3 mpixel image sensor produces raw digital video data at up to 30 fps. it has both ccp2 and mipi csi-2 video data interfaces selectable over the camera control interface (cci). the image data is digitized using an internal 10-bit column adc. the resulting 10-bit pixel data is output as 8-bit, 10-bit or 10-8 bi t compressed data and includes checksums and embedded codes for synchronization. the interf ace conforms to both the ccp2 and mipi csi-2 interface standards. the sensor is fully configurable through a cci serial interface. the module is available in a smop type package measuring 6.5 mm x 6.5 mm x 4.24 mm. it is designed to be used with a board mounted socket or flex. figure 1. vs6663cb camera module table 2. technical specification feature detail sensor technology img140 st?s 65 nm based cmos imaging process pixel size 1.75 m x 1.75 m analogue gain 24 db (max) dynamic range 60 db (typical) signal to noise 38 db (typical) snr10 value 50 lux supply voltage analogue: 2.6 v to 2.9 v digital: 1.68 v to 1.92 v average power consumption 30 fps 150 mw (typical) lens 51 hfov f/2.8 tv distortion <1% system attach socket or flex overview vs6663cb 8/64 doc id026749 rev 2 1.1 vs6663cb use in system with hard ware coprocessor the vs6663cb as an image sensor can be pa ired with an stmicroelectronics hardware accelerator. the coprocessor and the sensor together form a complete imaging system. figure 2 illustrates a typical system using vs6663cb. figure 2. vs6663cb in system with processor pixel array y-dec col adc power management video timing dig filters dark cal video engine cci te s t c t r l sys ctrl clk mngt pll vs6663cb ccp2 / csi-2 output data i/f ccp2 / csi-2 rx ccp2 / csi-2 rx input data i/f output coder mux bayer recon- struction scaler color engine color engine house cci master cci slave keeper mobile base band extclk xshut down cci xshut down cci ccp2 / csi-2 4 ch av doc id026749 rev 2 9/64 vs6663cb overview 47 the module's main function is to convert the viewed scene into a data stream. the companion processor?s function is to manage the sensor included in the module in order to produce the best possible pictures given the module's optics and the scene itself. the companion processor processes the data stream in to a form which is easily handled by up stream mobile baseband or multimedia processor (mmp) chipsets. the sensor supplies high-speed clock signal to the coprocessor and provides the embedded control sequences which allow the coprocessor to synchronize with the frame and line level timings. the coprocessor then performs the color processing on the raw image data from the sensor before supplying the final image data to the host. in a coprocessor architecture, a low speed clock (external clock) is sent by the host to both the vs6663cb and the coprocessor. this is used by the sensor in all phases of operation and by the coprocessor during the initial stages of system boot up. during streaming phase, the vs6663cb supplies the high-speed data qualification clock for the coprocessor. the high-speed clock is generated using the vs6663cb embedded pll and is provided as the continuous data qualification clock. 1.2 vs6663cb use in a system with software image processing the vs6663cb image sensor can also be directly connected to a baseband or multimedia processor. no dedicated coprocessor is used in this configuration. the image processing is done in software within the baseband processor. figure 3. vs6663cb in a system with software image processing pixel array y-dec col adc power management video timing dig filters dark cal cci test ctrl sys ctrl clk mngt pll vs6663cb mobile baseband processor xshutdown extclk ccp2 / csi-2 output data i/f 4 ch av overview vs6663cb 10/64 doc id026749 rev 2 1.3 reference documents table 3. reference documents title date mipi alliance standard for camera serial interface 2 (csi-2) v1.0 29-nov-2005 mipi alliance d-phy specification (v1.00.00) 14-may-2009 doc id026749 rev 2 11/64 vs6663cb device pinout 47 2 device pinout figure 4 shows the position of the pins on the module and table 4 provides the signal descriptions. figure 4. vs6663cb module pinout (viewed from bottom of camera module) table 4. pin description pad number pad name i/o type description power supplies 1 vcap pwr do not connect (1) 7 gnd pwr ground (combined) 2 vana pwr analog power 10 vdig pwr digital power system 3 xshutdown i power down control (2) 4 extclk i system clock input control 5 scl i serial communication clock 123456 7 8 9 10 11 12 tp tp tp tp tp tp tp xshutd datan datap vcap vana extclk scl sda vdig clkp clkn gnd tp device pinout vs6663cb 12/64 doc id026749 rev 2 6 sda i/o serial communication data data 8 clk- sublvds output output qualifying clock 9 clk+ sublvds output output qualifying clock 11 data- sublvds output serial output data 12 data+ sublvds output serial output data st test tp st test pins do not connect (3) 1. no connection should be made to vcap. 2. signal is active low. 3. test pins are not floating. table 4. pin description (continued) pad number pad name i/o type description doc id026749 rev 2 13/64 vs6663cb functional description 47 3 functional description 3.1 external clock 3.1.1 clock input type the external clock provided by the host to the vs6663cb must be a dc coupled square wave and may also be rc-filtered. figure 5. clock input types 3.1.2 pll and clock input the vs6663cb has an embedded pll block. this block generates all necessary internal clocks from an input range defined in table 5 . the value of the external clock frequency must be written to register 0x0136 (extclk_frequency_mhz). pad pad extclk extclk camera module host processor pad pad extclk extclk camera module host processor 1st option dc-coupled 2nd option dc-coupled and filtered pwrdn pwrdn pwrdn pwrdn table 5. system input clock frequency range minimum (mhz) maximum (mhz) 6 27 functional description vs6663cb 14/64 doc id026749 rev 2 3.2 device operating modes the mode changes in vs6663cb are shown in figure 6 . further details are provided in the following sections. figure 6. system state diagram streaming csi-2 sw-standby ccp2 sw-standby csi-2 hw-standby csi-2 power-off csi-2 streaming ccp2 cci cci cci cci cci cci xshutdown is high xshutdown is low power supplies on power supplies off xshutdown is low power supplies off doc id026749 rev 2 15/64 vs6663cb functional description 47 3.2.1 power-up procedure the digital and analog supply voltages can be powered up in any order, for example, vdig then vana or vana then vdig. on power-up the on-chip power-on reset cell ensures that the cci register values are initialized correctly to their default values. the extclk clock can either be initially low and then enabled during software standby mode or extclk can be a free running clock. the power-up sequence timing constraints are shown in table 6 . table 6. power-up sequence timing constraints symbol parameter min. max. units t0 vana rising ? vdig rising vana and vdig may rise in any order. the rising separation can vary from 0 ns to indefinite. ns t1 vdig rising ? vana rising ns t2 vdig / vana rising ? xshutdown rising xshutdown must rise later than or coincident with the later rising supply (vdig or vana) s t3 xshutdown ? first i 2 c transaction 2400 - extclk cycles t4 minimum number of extclk cycles prior to the first i 2 c transaction 2400 - extclk cycles t5 pll start up/lock time - 1 ms t6 entering streaming mode ? first frame start sequence (fixed part) -ms t7 entering streaming mode ? first frame start sequence (variable part) = integration time the delay is the coarse integration time value. functional description vs6663cb 16/64 doc id026749 rev 2 figure 7. vs6663cb power-up sequence for ccp2 t0 t1 t3 t4 t5 t6 vdig vana xshutdown extclk (free running) extclk (gated) cci clk+/- data+/- frame count register extclck may be free running or gated read device id configure device enter streaming 0xff 0x01 t2 t7 this is an example of vana rising after vdig high z (tri-state) lp00 (csi-2 mode) mode changed to ccp2 doc id026749 rev 2 17/64 vs6663cb functional description 47 figure 8. vs6663cb power-up sequence for csi-2 mode t6 extclk (free running) cci clk+/- data+/- frame count register extclk may be free running or gated read device id configure device enter streaming 0xff 0x01 high-speed tx t0 t1 t3 vdig vana xshutdown t2 this is an example of vana rising after vdig t4 extclk (gated) lp11 lp01 t5 t7 functional description vs6663cb 18/64 doc id026749 rev 2 3.2.2 power-down procedure the power-down sequence timing constraints are shown in table 7 . table 7. power-down sequence timing constraints for csi2 communications symbol parameter minimum maximum units t8 last i 2 c transaction to software standby - 1 frame t9 last i 2 c transaction or mipi frame end to xshutdown falling 512 - clock cycles t10 xshutdown to vana/vdig falling xshutdown must fall at the same time as, or earlier than, both power supplies (vdig and vana) t11 vana to vdig or vdig to vana falling vana and vdig may fall in any order, the rising separation can vary from 0 ns to indefinite doc id026749 rev 2 19/64 vs6663cb functional description 47 figure 9. vs6663cb power-down sequence for csi-2 mode extclk (free running) extclk (gated) cci clk+/- data+/- extclk may be free running or gated configure device t8 high-speed tx t11 t10 vdig xshutdown high-speed tx stop streaming vana this is an example of vana falling after vdig lp11 t9 lp11 csi output is disabled after xshutdown=0 or clock is stopped functional description vs6663cb 20/64 doc id026749 rev 2 3.2.3 internal power-on reset (por) the vs6663cb internally performs a power-on reset (por) when the digital supply rises through the trigger level, vtrig_rising. similarly, if the digital power supply falls through the trigger level, vtrig_fa lling, then the power-on reset will also trigger. figure 10. por timing por cell output digital power supply, vdig v trig_rising burst > t2 t1 t1 t3 v trig_falling burst < t4 burst > t5 burst > t5 < table 8. por cell characteristics symbol constraint minimum typical maximum units t1 vdig rising crossing vtrig_rising ? internal reset being released. 20.7 30.7 50.7 s t2 minimum vdig spike width below vtrig_falling which is considered to be a reset when por cell output high. 1.25 2.1 6.9 s t3 (1) vdig falling crossing vtri g_falling - internal reset active. 1.25 2.1 6.9 s t4 minimum vdig spike width below vtrig_falling which is considered to be a reset when por cell output low. 1.5 2.1 6.9 s t5 minimum vdig spike width above vtrig_rising which is considered to be a supply is stable when por cell output low. while the por cell output is low, all vdig spikes above vtrig_rising which are less than t5 must be ignored. 20.7 30.7 50.7 ns vtrig_rising vdig rising trigger voltage. 429 755 944 mv vtrig_falling vdig falling trigger voltage. 401 725 904 mv 1. the device could be reset by any vdig voltage excursion falling below vtrig_fal ling and will always be reset by a vdig voltage excursion below vtrig_falling of > 0.5 s doc id026749 rev 2 21/64 vs6663cb functional description 47 3.2.4 power-off the power-off state is defined as either or both of the digital and analog supplies not present. 3.2.5 hardware standby this is the lowest power consumption mode. cci communications are not supported in this mode. the pll and the vi deo blocks are powered down. this state is entered by pulling the control pin xshutdown down (act ive low). all registers are returned to their default values 3.2.6 software standby software standby mode preserves the contents of the cci register map. cci communications are supported in this mode. the software standby mode is selected using a serial interface command. if this state is entered from hardware standby the data pads remain high impedance. if this state is entered from streaming then the data pads go high impedance at the end of the current frame. the in ternal video timing is reset to the start of a video frame in preparation for the enabling of active video. the values of the serial interface registers like exposure and gain are preserved. the system clock must remain active when communicating with the sensor. this state is entered by releasing the device from hard reset by setting xshutdown high, writing 0x00 to the mode control register (0x0100) or commanding a soft reset by writing 0x01 to the software reset register (0x0103). note: after a soft reset or the tr ansition of xshutdown to high, a ll registers are returned to their default values. 3.2.7 streaming the vs6663cb streams live video. this mode is entered by writing 0x01 to the mode control register (0x0100). 3.2.8 dark calibration algorithm vs6663cb runs an automatic dark calibration algorithm on the raw image data to control the video offsets caused by dark current. this ensures that a high quality image is output over a range of operating conditions. first fr ame dark level is correctly calibrated, for subsequent frames the adjustment of the dark le vel is damped by a leaky integrator function to avoid possible frame to frame flicker. camera control interface (cci) vs6663cb 22/64 doc id026749 rev 2 4 camera control interface (cci) this chapter specifies the camera control in terface (cci). the i 2 c-type interface uses 1.8 v i/o with two signals: serial data line (sda) and serial clock line (scl). cci is used for control data transfer. clock signal (scl) generati on is performed by the master device (the camera module is a slave device). the master device initiates data transfer. the cci bus on the camera module has a maximum speed of 400 kbits/s and has a software switchable device address. any internal register that can be written to, can also be read from. there are also read only registers that contain device status informatio n, (for example, design revision details). a read instruction from an un-used register location will return the value 0x00. a read instruction from the manufacturers specific registers may return any value. a write instruction to a reserved or unused register location is illegal and the effect of such a write is undefined. it is the responsibility of the host syst em to only write to re gister locations which have been defined. 4.1 valid register data types the contents of the registers can represent a number of different data types (see table 9 ). the register map uses this coding to help with the interpretation of the contents of each register. table 9. valid register data types data type name range description 8ui 8-bit unsigned integer 0 to 255 - 8si 8-bit signed integer -128 to 127 two?s complement notation 16ui 16-bit unsigned integer 0 to 65535 - 16si 16-bit signed integer -32768 to 32767 two?s complement notation 16ur 16-bit unsigned ireal 0 to 255.99609375 08.08 fixed point number. 8 integer bits (ms byte), 8 fractional bits (ls byte) 16sr 16-bit signed ireal -128 to 127.9960375 two?s complement notation, 8 fractional bits 32sf 32-bit ieee floating-point number as per ieee 754 as per ieee 754. 1 sign bit, 8 exponent bits, 23 fractional bits 8c or 16c 8-bit or 16-bit coded - this indicates that the value is decoded to select one of several functions or modes. 8b or 16b 8 or 16 bits - each bit represents a specific function or mode. doc id026749 rev 2 23/64 vs6663cb camera control interface (cci) 47 4.2 register map 4.2.1 general status re gisters [0x0000 to 0x001f] table 10. general status registers [0x0000 to 0x001f] index byte register name data type default type comment 0x0000 hi model_id 16ui 02.97 ro camera model identification 0x0297 = 663 10 0x0001 lo 0x0002 revision_number_major 8ui 04 ro revision identifier of the camera 0x0003 manufacturer_id 8c 01 ro manufacturer id: st micro 0x0004 smia_version 8c 0a ro 0x0a: smia 1.0 0x0005 frame_count 8ui ff ro frame count increments from 1 to 254 when streaming. when moving from video to sleep the frame count is reset to 255. the frame count is also reset to 255 after a soft reset (register 0x0103). 0x0006 pixel_order 8c 00 ro color pixel readout order. defines the order of the color pixel readout. changes with mirror and flip (register 0x0101). 0x00 - gr/bg - normal 0x01 - rg/gb - horizontal mirror 0x02 - bg/gr - vertical flip 0x03 - gb/rg - vertical flip and horizontal mirror 0x0008 hi data_pedestal 16ui 00.40 ro the video data is offset by 64 0x0009 lo 0x000c pixel_depth 8ui 0a ro pixel data resolution. for vs6663cb the pixel depth is 10 bits. camera control interface (cci) vs6663cb 24/64 doc id026749 rev 2 4.2.2 frame format descripti on registers [0x0040 to 0x007f] for a full description of the frame format description refer to chapter 5: video data interface on page 36 . 4.2.3 analog gain descripti on registers [0x0080 to 0x0093] for a full description of the analog gain description registers refer to chapter 6: video timing on page 39 . table 11. frame format description registers [0x0040 to 0x007f] index byte register name data type default type comment 0x0040 frame_format_model_type 8c 01 ro generic frame format. 0x01: 2-byte data format. 0x0041 frame_format_model_subtype 8c 12 ro contains the number of 2-byte data format descriptors used. upper nibble defines the number of column descriptors (1). the lower nibble defines the number of row descriptors (2) 0x0042 hi frame_format_descriptor_0 16c 55.10 ro pixel data code: 5 (visible columns) number of pixels : readout dependent (maximum of 1296) number of pixels: 1296 0x0043 lo 0x0044 hi frame_format_descriptor_1 16c 10.02 ro pixel data code: 1 (embedded data lines) number of status lines:2 0x0045 lo 0x0046 hi frame_format_descriptor_2 16c 53.d0 ro pixel data code: 5 (visible lines) number of pixels: readout dependent (maximum of 976) number of pixels: 976 0x0047 lo table 12. analog gain description [0x0080 to 0x0093] index byte register name data type default type comment 0x0080 hi analogue_gain_capability 16b 00.00 ro analog gain capability 0 ? single global analog gain only 0x0081 lo 0x0084 hi analogue_gain_code_min 16ui 00.00 ro minimum recommended analog gain code, that is, 0 (x1 gain) 0x0085 lo 0x0086 hi analogue_gain_code_max 16ui 00.f0 ro maximum recommended analog gain code, that is, 240 (x16 gain) 0x0087 lo 0x0088 hi analogue_gain_code_step 16ui 00.10 ro analog gain code step size 0x0089 lo doc id026749 rev 2 25/64 vs6663cb camera control interface (cci) 47 4.2.4 data format descripti on registers [0x00c0 to 0x00c7] 0x008a hi analogue_gain_type 16ui 00.00 ro analog gain type 0x008b lo 0x008c hi analogue_gain_m0 16si 00.00 ro analog gain m0 constant. m0 = 0 0x008d lo 0x008e hi analogue_gain_c0 16si 01.00 ro analog gain c0 constant. c0 = 256 0x008f lo 0x0090 hi analogue_gain_m1 16si ff.ff ro analog gain m1 constant. m1 =-1 0x0091 lo 0x0092 hi analogue_gain_c1 16si 01.00 ro analog gain c1 constant c1 = 256 0x0093 lo table 12. analog gain description [0x0080 to 0x0093] (continued) index byte register name data type default type comment table 13. data format description registers [0x00c0 to 0x00c7] index byte register name data type default type comment 0x00c0 data_format_model_type 8ui 01 ro 2-byte generic data format model. always 0x01 0x00c1 data_format_model_subtype 8ui 03 ro number of descriptors, that is, 3 0x00c2 hi data_format_descriptor_0 16ui 08.08 ro top 8-bits of internal pixel data transmitted as raw8. 0x00c3 lo 0x00c4 hi data_format_descriptor_1 16ui 0a.0a ro top 10-bits of internal pixel data transmitted as raw 10. 0x00c5 lo 0x00c6 hi data_format_descriptor_2 16ui 0a.08 ro compress top 10-bits of internal pixel data to 8. transmitted as raw 8 mode. 0x00c7 lo camera control interface (cci) vs6663cb 26/64 doc id026749 rev 2 4.2.5 setup registers [0x0100 to 0x01ff] table 14. setup registers [0x0100 to 0x01ff] index byte register name data type default type comment 0x0100 mode_select 8ui 00 rw mode select 0x00 - software standby 0x01 - streaming refer to section 3.2: device operating modes on page 14 0x0101 image_orientation 8b 00 rw image orientation, that is, horizontal mirror and vert ical flip. bit 0: 0 - no mirror, 1 - horizontal mirror enable bit 1: 0 - no flip, 1 - vertical flip enable 0x0103 software_reset 8ui 00 rw software reset. setting this register to 1 resets the sensor to its power up defaults. the value of this bit is also reset 0x00 - normal 0x01 - soft reset refer to section 3.2: device operating modes on page 14 0x0104 grouped_parameter_hold 8ui 00 rw the grouped parameter hold register disables the consumption of integration, gain and video timing parameters 0x00 - consume parameters as normal 0x01 - hold parameters refer to section 6.3.3: integration and gain parameter retiming on page 46 0x0105 mask_corrupted_frames 8ui 00 rw setting this register to 1 prevents the sensor outputing frames that have been corrupted by video timing parameter changes. 0x00 - normal 0x01 - mask corrupted frames 0x0110 csi_channel_identifier 8ui 00 rw the dma (ccp2) or virtual (csi2) channel identifier valid range: 0-7 for ccp2 valid range: 0-3 for csi-2 0x0111 csi_signalling_mode 8ui 02 rw 0x00 - ccp2 data/clock signalling: 0x01 - ccp2 data/strobe signalling: 0x02 - csi-2: this register should not be changed while the device is streaming data. doc id026749 rev 2 27/64 vs6663cb camera control interface (cci) 47 4.2.6 integration time and ga in registers [0x0200 to 0x02ff] these registers are used to control the image exposure. see section 6.3: exposure and gain control on page 45 for more information. 0x0112 hi csi_data_format 16ui 0a.0a rw the msb contains the bit width of the uncompressed pixel data. the lsb contains the bit width of the compressed pixel data. 0a.0a - raw10 mode 0a.08 - 10-8 compressed mode 08.08 - raw8 mode 0x0113 lo 0x0114 csi_lane_mode 8ui 00 rw number of data lanes in use 00 - 1-lane 0x0115 csi2_10_to_8_dt 8ui 30 rw csi-2 data type for 10-8 compression 0x0120 gain_mode 8ui 00 ro 0x00 ? global analog gain. vs6663cb supports only global gain modes. 0x0136 hi extclk_frequency_mhz 8.8ur 06.00 rw frequency of external crystal 0x0137 lo table 14. setup registers [0x0100 to 0x01ff] (continued) index byte register name data type default type comment table 15. integration time and gain registers [0x0200 to 0x02ff] index byte register name data type default type comment 0x0200 hi fine_integration_time 16ui 01.4c rw fine integration time (pixels) 0x0201 lo 0x0202 hi coarse_integration_time 16ui 00.00 rw c oarse integration time (lines). 0x0203 lo 0x0204 hi analogue_gain_code_global 16ui 00.00 rw global analog gain parameter (coded). see section 6.3.1: gain model on page 45 for details of how to use this parameter. 0x0205 lo 0x020e hi digital_gain_greenr 16ur 01.00 rw gain code for greenr channel 0x020f lo 0x0210 hi digital_gain_red 16ur 01.00 rw gain code for red channel 0x0211 lo 0x0212 hi digital_gain_blue 16ur 01.00 rw gain code for blue channel 0x0213 lo 0x0214 hi digital_gain_greenb 16ur 01.00 rw gain code for greenb channel 0x0215 lo camera control interface (cci) vs6663cb 28/64 doc id026749 rev 2 4.2.7 video timing re gisters [0x0300 to 0x03ff] for a full description of the video timing registers refer to chapter 6: video timing on page 39 . table 16. video timing registers [0x0300 to 0x03ff] index byte register name data type default type comment 0x0300 hi vt_pix_clk_div 16ui 00.0a rw video timing clock divider value: 10 0x0301 lo 0x0302 hi vt_sys_clk_div 16ui 00.01 rw video timing clock divider value: 1 0x0303 lo 0x0304 hi pre_pll_clk_div 16ui 00.01 rw pre pll clock divider value value: 1 0x0305 lo 0x0306 hi pll_multiplier 16ui 00.85 rw pll multiplier value value: 133 0x0307 lo 0x0340 hi frame_length_lines 16ui 03.f0 rw frame length units: lines value: 1008 0x0341 lo 0x0342 hi line_length_pck 16ui 0a.50 rw line length units: pixel clocks value: 2640 0x0343 lo 0x0344 hi x_addr_start 16ui 00.00 rw x-address of the top left corner of the visible pixel data units: pixels value: 0 0x0345 lo 0x0346 hi y_addr_start 16ui 00.00 rw y-address of the top left corner of the visible pixel data. must be modulo 4 for correct operation of device. units: lines value: 0 0x0347 lo 0x0348 hi x_addr_end 16ui 05.0f rw x-address of the bottom right corner of the visible pixel data units: pixels value: 1295 0x0349 lo 0x034a hi y_addr_end 16ui 03.cf rw y-address of the bottom right corner of the visible pixel data units: lines value = 975 0x034b lo 0x034c hi x_output_size 16ui 05.10 rw width of image data output from the sensor module units: pixels value: 1296 0x034d lo doc id026749 rev 2 29/64 vs6663cb camera control interface (cci) 47 4.2.8 image compression registers [0x0500 to 0x0501] 4.2.9 test pattern re gisters [0x0600 to 0x0611] 0x034e hi y_output_size 16ui 03.d0 rw height of image data output from the sensor module units: lines value: 976 0x034f lo 0x0380 hi x_even_inc 16ui 00.01 rw increment for even pixels units: pixels 0x0381 lo 0x0382 hi x_odd_inc 16ui 00.01 rw increment for odd pixels units: pixels 0x0383 lo 0x0384 hi y_even_inc 16ui 00.01 rw increment for even pixels units: pixels 0x0385 lo 0x0386 hi y_odd_inc 16ui 00.01 rw increment for odd pixels units: pixels 0x0387 lo table 16. video timing registers [0x0300 to 0x03ff] (continued) index byte register name data type default type comment table 17. image compression registers [0x0500 to 0x0501] index byte register name data type default type comment 0x0500 hi compression_mode 16ui 00.01 ro 1 ? dpcm/pcm compression (simple predictor) 0x0501 lo table 18. test pattern registers [0x0600 to 0x0611] index byte register name data type default type comment 0x0600 hi test_pattern_mode 16c 00.00 rw 0 ? normal operation (default) 1 ? solid color bars 2 ? 100% color bars 3 ? fade to grey? color bars 4 - pn9 5 to 255 - reserved 256 to 65535 - manufacturer specific 0x0601 lo 0x0602 hi test_data_red 16ui 00.00 rw the test data used to replace red pixel data. range 0 to 1023. (1) 0x0603 lo 0x0604 hi test_data_greenr 16ui 00.00 rw the test data used to replace green pixel data on rows that also have red pixels. valid range 0 to 1023. (1) 0x0605 lo camera control interface (cci) vs6663cb 30/64 doc id026749 rev 2 4.2.10 binning regi sters [0x0900 to 0x0902] 0x0606 hi test_data_blue 16ui 00.00 rw the test data used to replace blue pixel data. range 0 to 1023. (1) 0x0607 lo 0x0608 hi test_data_greenb 16ui 00.00 rw the test data used to replace green pixel data on rows that also have blue pixels. range 0 to 1023. (1) 0x0609 lo 0x060a hi horizontal_cursor_width 16ui 00.00 rw defines the width of the horizontal cursor (in pixels). 0x060b lo 0x060c hi horizontal_cursor_position 16ui 00.00 rw defines the top edge of the horizontal cursor. 0x060d lo 0x060e hi vertical_cursor_width 16ui 00.00 rw defines the width of the vertical cursor (in pixels). 0x060f lo 0x0610 hi vertical_cursor_ position 16ui 00.00 rw defines the left hand edge of the vertical cursor. maximum value = 0xffff a value of 0xffff switches the vertical cursor into automatic mode where it automatically advances every frame. 0x0611 lo 1. some clipping of these values may occu r to prevent false sync codes being generated table 18. test pattern registers [0x0600 to 0x0611] (continued) index byte register name data type default type comment table 19. binning registers [0x0900 to 0x0902] index byte register name data type default type comment 0x0900 binning_mode 8ui 00 rw binning mode 0 - disable 1 - enable doc id026749 rev 2 31/64 vs6663cb camera control interface (cci) 47 4.2.11 integration time and gain para meter limit register s [0x1000 to 0x10ff] these registers are used to define exposure limits for the integrat ion control registers (0x200 - 0x203). see section 6.3: exposure and gain control on page 45 for more information. table 20. integration time and gain para meter limit registers [0x1000 to 0x10ff] index byte register name data type default type comment 0x1000 hi integration_time_capability 16ui 00.01 ro this device supports coarse and fine integration. 0x1001 lo 0x1004 hi coarse_integration_time_ min 16ui 00.00 ro minimum coarse integration time. line periods. 0x1005 lo 0x1006 hi coarse_integration_time_ max_margin 16ui 00.07 ro current frame length ? current max coarse exposure. line periods. 0x1007 lo 0x1008 hi fine_integration_time_min 16ui 01.4c ro minimum fine integration time. 332 pixel periods. 0x1009 lo 0x100a hi fine_integration_time_ max_margin 16ui 06.df ro current line length - current max fine exposure. 1759 pixel periods. 0x100b lo 0x1080 hi digital_gain_capability 16ui 00.01 ro vs6663cb supports digital gain 0x1081 lo 0x1084 hi digital_gain_min 16ur 00.01 ro 0.0039 minimum 0x1085 lo 0x1086 hi digital_gain_max 16ur 01.ff ro 1.996 maximum 0x1087 lo 0x1088 hi digital_gain_step_size 16ur 00.01 ro 0.0039 step size 0x1089 lo camera control interface (cci) vs6663cb 32/64 doc id026749 rev 2 4.2.12 video timing parameter li mit registers [0x1100 to 0x11ff] for a full description of the video timi ng parameter limit registers refer to chapter 6: video timing on page 39 . table 21. video timing parameter li mit registers [0x1100 to 0x11ff] index byte register name data type default type comment 0x1100 hi min_ext_clk_freq_mhz 32sf 40.c0 00.00 ro minimum external clock frequency units: mhz value: 6.0 0x1101 3rd 0x1102 2nd 0x1103 lo 0x1104 hi max_ext_clk_freq_mhz 32sf 41.d8 00.00 ro maximum external clock frequency units: mhz value: 27.0 0x1105 3rd 0x1106 2nd 0x1107 lo 0x1108 hi min_pre_pll_clk_div 16ui 00.01 ro minimum pre pll divider value value: 1 0x1109 lo 0x110a hi max_pre_pll_clk_div 16ui 00.04 ro maximum pre pll divider value value: 4 0x110b lo 0x110c hi min_pll_ip_freq_mhz 32sf 40.c0 00.00 ro minimum pll input clock frequency units: mhz value: 6.0 0x110d 3rd 0x110e 2nd 0x110f lo 0x1110 hi max_pll_ip_freq_mhz 32sf 41.40 00.00 ro maximum pll input clock frequency units: mhz value: 12.0 0x1111 3rd 0x1112 2nd 0x1113 lo 0x1114 hi min_pll_multiplier 16ui 00.19 ro minimum pll multiplier value: 25 0x1115 lo 0x1116 hi max_pll_multiplier 16ui 00.85 ro maximum pll multiplier value: 133 0x1117 lo 0x1118 hi min_pll_op_freq_mhz 32sf 43.96 00.00 ro minimum pll output clock frequency units: mhz value: 300.0 0x1119 3rd 0x111a 2nd 0x111b lo doc id026749 rev 2 33/64 vs6663cb camera control interface (cci) 47 0x111c hi max_pll_op_freq_mhz 32sf 44.48 00.00 ro maximum pll output clock frequency units: mhz value: 800.0 0x111d 3rd 0x111e 2nd 0x111f lo 0x1120 hi min_vt_sys_clk_div 16ui 00.01 ro minimum video-timi ng system clock divider value value: 1 0x1121 lo 0x1122 hi max_vt_sys_clk_div 16ui 00.04 ro maximum video-timing system clock divider value value: 4 0x1123 lo 0x1124 hi min_vt_sys_clk_freq_mhz 32sf 42.96 00.00 ro minimum video-timi ng system clock frequency units: mhz value: 75.0 this value is 80 mhz in csi2 mode. 0x1125 3rd 0x1126 2nd 0x1127 lo 0x1128 hi max_vt_sys_clk_freq_mhz 32sf 44.48 00.00 ro maximum video-timing system clock frequency units: mhz value: 800.0 the maximum value is 640 mhz in ccp mode. 0x1129 3rd 0x112a 2nd 0x112b lo 0x112c hi min_vt_pix_clk_freq_mhz 32sf 40.f0 00.00 ro minimum video-timing pixel clock frequency units: mhz value: 7.5 0x112d 3rd 0x112e 2nd 0x112f lo 0x1130 hi max_vt_pix_clk_freq_mhz 32sf 42.a0 00.00 ro maximum video-timing pixel clock frequency units: mhz value: 80.0 0x1131 3rd 0x1132 2nd 0x1133 lo 0x1134 hi min_vt_pix_clk_div 16ui 00.08 ro minimum video-timing pixel clock divider value: 8 0x1135 lo 0x1136 hi max_vt_pix_clk_div 16ui 00.0a ro maximum video-timing pixel clock divider value: 10 0x1137 lo 0x1140 hi min_frame_length_lines 16ui 00.d0 ro minimum frame length allowed. value = 208 units: lines 0x1141 lo table 21. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment camera control interface (cci) vs6663cb 34/64 doc id026749 rev 2 0x1142 hi max_frame_length_lines 16ui ff.ff ro maximum possible number of lines per frame. value = 65535 units: lines 0x1143 lo 0x1144 hi min_line_length_pck 16ui 0a.50 ro minimum line length allowed. value = 2640 units: pixel clocks 0x1145 lo 0x1146 hi max_line_length_pck 16ui 3f.ff ro maximum possible number of pixel clocks per line. value = 16383 units: pixel clocks 0x1147 lo 0x1148 hi min_line_blanking_pck 16ui 05.30 ro minimum line blanking time in pixel clocks value = 1328 units: pixel clocks 0x1149 lo 0x114a hi min_frame_blanking_lines 16ui 00.0e ro minimum frame blanking in video lines = 14 0x114b lo 0x114c hi min_linelength_pck_step_size 16ui 00.01 ro mi nimum step size of line length pck 0x114d lo 0x1180 hi x_addr_min 16ui 00.00 ro minimum x-address of the addressable pixel array value: always 0 0x1181 lo 0x1182 hi y_addr_min 16ui 00.00 ro minimum y-address of the addressable pixel array value: always 0 0x1183 lo 0x1184 hi x_addr_max 16ui 05.0f ro maximum x-address of the addressable pixel array value = 1295 0x1185 lo 0x1186 hi y_addr_max 16ui 03.cf ro maximum y-address of the addressable pixel array value = 975 0x1187 lo 0x1188 hi min_x_output_size 16ui 01.00 ro minimum x output size in pixels. value: 256 0x1189 lo 0x118a hi min_y_output_size 16ui 00.c0 ro minimum y output size in pixels. value: 192 0x118b lo 0x118c hi max_x_output_size 16ui 05.10 ro maximum x output size in pixels. value: 1296 0x118d lo 0x118e hi max_y_output_size 16ui 03.d0 ro maximum y output size in pixels: value: 976 0x118f lo table 21. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment doc id026749 rev 2 35/64 vs6663cb camera control interface (cci) 47 4.2.13 binning capability registers [0x1700 to 0x1713] 0x11c0 hi min_even_inc 16ui 00.01 ro minimum increment for even pixels 0x11c1 lo 0x11c2 hi max_even_inc 16ui 00.01 ro maximum increment for even pixels 0x11c3 lo 0x11c4 hi min_odd_inc 16ui 00.01 ro minimum increment for odd pixels 0x11c5 lo 0x11c6 hi max_odd_inc 16ui 00.01 ro maximum increment for odd pixels 0x11c7 lo table 21. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment table 22. binning capability registers [0x1700 to 0x1713] index byte register name data type default type comment 0x1700 hi min_frame_length_lines_bin 16ui 00.d0 ro minimum frame length allowed in binning mode. units: lines 0x1701 lo 0x1702 hi max_frame_length_lines_bin 16ui ff.ff ro maximum possible number of lines per frame allowed in binning mode. value = 65535 units: lines 0x1703 lo 0x1704 hi min_line_length_pck_bin 16ui 0a.50 ro minimum line length allowed in binning mode. value = 2640 units: pixel clocks 0x1705 lo 0x1706 hi max_line_length_pck_bin 16ui 3f.ff ro maximum possible number of pixel clocks per line allowed in binning mode. units: pixel clocks 0x1707 lo 0x1708 hi min_line_blanking_pck_bin 16ui 05.30 ro minimum line blanking time in pixel clocks allowed in binning mode. value = 1328 units: pixel clocks 0x1709 lo 0x170a hi fine_integration_time_min_bin 16ui 01.24 ro minimum fine integration time. pixel periods allowed in binning mode. 0x170b lo 0x170c hi fine_integration_time_max_ margin_bin 16ui 07.ea ro current line length ? current max fine exposure allowed in binning mode. pixel periods. 0x170d lo video data interface vs6663cb 36/64 doc id026749 rev 2 5 video data interface the video stream which is output from the vs6663cb through the compact camera port (ccp) or camera serial interface (csi) c ontains both video data and other auxiliary information. this chapter describes the frame formats. the vs6663cb is mipi csi-2 version 1.00 and d-phy 1.0 compliant. the selection of the video data forma t is controlled using the register csi_signalling_mode (0x0111): 0 - ccp2 data/clock 1 - ccp2 data/strobe 2 - csi-2 (default) changing the video data format must be performe d when the sensor is in software standby. ? the csi-2 link supports the transmission of ra w bayer data at 1.3 mpixel resolution up to 30 frame/s at 10-bit resolution. ? the ccp link supports the transmission of raw bayer data at 1.3 mpixel resolution up to 30 frame/s using10-8bit compressed data or 24 frame/s at 10-bit resolution. ? the vs6663cb has one csi-2 data lane capable of transmitting at 800 mbps. ? the vs6663cb ccp lane is capable of transmitting at 640 mbps. ? the csi-2 data lane transmitter supports: ? unidirectional master ?hs-tx ? lp-tx (ulps) ? cil-muyn function ? the csi-2 clock lane transmitter supports: ? unidirectional master ?hs-tx ? lp-tx (ulps) ? cil-mcnn function doc id026749 rev 2 37/64 vs6663cb video data interface 47 5.1 frame format the frame format for the vs6663cb is described by the frame format description registers in table 11 on page 24 . for ccp2 this results in a frame as shown in figure 11 and for csi- 2 it results in a frame as shown in figure 12 . figure 11. vs6663cb ccp2 frame format figure 12. vs6663cb csi-2 frame format embedded data lines the embedded data lines provide a mechanism to embed non-image data such as sensor configuration details within the output data stream. the number of embedded data lines at the start and end of the frame is specified as part of the frame format description. vs6663cb has two embedded data lines. interline padding interframe padding bayer pixel data ccp2 embedded line start codes ccp2 embedded checksum codes ccp2 embedded line end codes fe fs 2 embedded data lines frame start code frame end code bayer pixel data embedded data frame start packet frame end packet line blanking packet footer (pf) packet header (ph) frame blanking fe fs video data interface vs6663cb 38/64 doc id026749 rev 2 dummy pixel data this is invalid pixel data. the receiver should always ignore dummy pixel data. the vs6663cb has 0 dummy columns. visible pixel data the visible pixels contain valid image data.the correct integration time and analog gain for the visible pixels is specified in the blank lines at the start of the frame.the number of visible pixels can be varied with the requested frame size. dark pixel data (light shielded pixels) the vs6663cb has 0 dark pixels. black pixel data (zero integration time) the vs6663cb has 0 black pixels. manufacturer specific pixel data the vs6663cb has 0 manufacturer specific pixels. interline padding/line blanking during interline padding all bits in the da ta stream in a ccp2 frame are set to 1. in a csi-2 frame there is no concept of line blanking being transmitted, the sensor will simply spend a longer time in the lp state between active line data. interframe padding / frame blanking during interframe padding all bits in the data stream in a ccp2 frame are set to 1. in a csi-2 frame there is no concept of fram e blanking being transmitt ed, the sensor will simply spend a longer time in the lp state at the end of the active data for a frame. doc id026749 rev 2 39/64 vs6663cb video timing 47 6 video timing 6.1 output size the vs6663cb has the following methods available to achieve the required output size, these can be used independently or in conjunction with any other: ? analog crop, see section 6.1.1 ? binning, see section 6.1.2 ? output crop, see section 6.1.3 note: the vs6663cb does not support subsampling. the programmable image size and output si ze are independent functions. it is the responsibility of the ho st to ensure that these function s are programmed correctly for the intended application. figure 13. data flow 6.1.1 analog crop the native size for the vs6663cb is 1280x 96 0, the maximum addressable array is 1296 x 976 which gives eight border pixels for the co lor reconstruction algorithms to use at the edges of the array. by programming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers it is possible to use the full size of the array as yo u would do for a native size output or you can select a ?window of interest?. the addressed re gion of the array is used in any subsequent binning operation. output crop analog crop binning imaging array video timing vs6663cb 40/64 doc id026749 rev 2 figure 14. analog crop the host must ensure the following rules are kept: ? the end address must be greater than the start address ? the x and y start addresses are restricted to even numbers only, and the x and y end addresses are restricted to odd numbers only, to ensure that there is always a even number of pixels read-out 6.1.2 binning the vs6663cb also has a binning mode that offe rs a reduced size full field of view image. the binning mode averages row and column pixel data. the binning mode results in a reduced number of lines and so can be used to give a higher image frame rate. compared to subsampling, binning makes use of the light gathered from the whole pixel array and it re sults in higher image quality. the binning mode will scale by 2x2 in the x and y direction. entering and exiting binning mode may or may not be performed when the sensor is in software standby. table 23 summarizes the register setting for enabling binning mode. (the x/y_odd_inc registers are automatically set and do not require to be set by the user.) y_addr_max = 975 x_addr_max = 1295 y_addr_min = 0 x_addr_min = 0 x_addr_max, y_addr_max x_addr_end, y_addr_end addressed pixel array region x_addr_start, y_addr_start x_addr_min, y_addr_min table 23. binning register settings register address normal binning 2x2 binning_mode 0x0900 0 1 doc id026749 rev 2 41/64 vs6663cb video timing 47 6.1.3 output crop the x_output_size and y_output_size registers are not intended as the primary cropping controls. they are intended to define the position of the le/fe codes in the ccp2 data frame so that the sensor does not need to calculate this bas ed on analog crop or binning settings. it should be expected that the host will set the output size s to exactly encl ose the output image data. if the host should not do this, the vs6663cb treats the output size as being calculated from the top left hand corner of the output array. so in the case where output sizes are smaller than the output data, the data shall be cropped from its right-hand and lower limits. in the case where larger than the output data, the lines shall be padded out to the defined output size with undefined data. figure 15. output size within a ccp2 data frame the number of pixels between the line start and the line end sync codes for: ? raw8 is a multiple of 4 pixels ? raw10 is a multiple of 4 pixels for cs i-2 and a multiple of 16 pixels for ccp2 the host must control the x_output_size to ensure that the above criteria is met. ccp2 output active line length interline padding interframe padding x_output_size y_output_size output data ccp2 embedded checksum codes ccp2 embedded line end codes fe fs 2 embedded data lines ccp2 embedded line start codes video timing vs6663cb 42/64 doc id026749 rev 2 6.2 video timing this section specifies the timing for the image data that is readout from the pixel array and the output image data. these are not necessarily the same size. the application of all of the video timing read/w rite parameters must be re-timed to the start of frame boundary to ensure that the parameters are consistent within a frame. the video stream which is output from the vs6663cb contains both vi deo data and other auxiliary information. 6.2.1 pll block the vs6663cb contains a phase locked loop (pll) block, which generates all the necessary internal clo cks from the external clock input. ch anges to the pll settings on the vs6663cb will only be consumed on the softwa re standby to str eaming mode transition. figure 16 shows the internal functional blocks, which define the relationship between the external input clock frequency and the pixel clock frequency. the majority of the logic withi n the device is clocked by vt_sys_clk however the cci block is clocked by the external input clock. figure 16. clock relationship the equation relating the input clock fr equency to pixel clock frequencies is: 6.2.2 framerate the framerate of the array readout and theref ore the output framerate is governed by the line length, frame length and the video timing pixel clock frequency. ? line length is specified as a number of pixel clocks, line_length_pck ? frame length is specified as a number of lines, frame_length_lines ? video timing pixel clock is specified in mhz, vt_pix_clk_freq_mhz max. 800 mhz min. 300 mhz min. 25 max. 133 pll_multiplier max. 12 mhz min. 6 mhz pre_pll_ clk_div range 1, 2, 4 max. 27 mhz min. 6 mhz ext. input clock external input clock ext_clk_freq_mhz pll input clock pll_ip_clk_freq_mhz pll output clock pll_op_clk_freq_mhz video timing pixel clock vt_pix_clk_freq_mhz video timing system clock vt_sys_clk_freq_mhz max. 800 mhz (2) min. 75 mhz (1) range 1, 2, 4 vt_sys_clk _div vt_pix_clk _div max. 80 mhz min. 7.5 mhz min. 8 max. 10 1. the minimum vt_sys_clk_freq_mhz is 80 mhz in csi-2 mode. 2. the maximum vt_sys_clk_freq_mhx is 640 mhz in ccp mode. vt_pix_clk_freq_mhz ext_clk_freq_mhz pll_multiplier pre_pll_clk_div vt_sys_c lk_div vt_pix_clk_div ------------------------------------------------------------------------------------------------------------------------------- - = doc id026749 rev 2 43/64 vs6663cb video timing 47 the equation relating the framerate to the line length, frame length and the video timing pixel clock frequency is: table 24 provides examples of frame timing for ra w10 csi-2 mode for 30 fps at a variety of external clock frequencies. 6.2.3 bayer pattern the three color (red, green, blue) filters are ar ranged over the pixel array in a repeated 2x2 arrangement known as the bayer pattern. when the sensor array is read, the output order of red, green, blue depends on the settings of vertical flip and horizontal mirror. figure 17 shows the read-out order for the default settings of vertical flip and horizontal mirror turned off. vertical flip changes the fi rst line to be output from a green/red line to a blue/green line and horizontal mirror change s the sequence within a line, for example, green/red to red/green. as shown in figure 17 , the first pixel to be readout fr om the imaging array will be green followed by red. table 24. external clock frequency examples - 1.3 mpixel resolution raw10 30 fps ext clk freq pre-pll clk div pll multiplier vt sys clk div vt pixel clk div vt pixel clk freq line length frame length mhz integer integer (dec) integer integer mhz pixel clks lines (dec) 9.60 1 83 1 10 79.68 2640 1006 12.00 2 133 1 10 79.80 2640 1007 13.00 2 123 1 10 79.95 2640 1009 framerate vt_pix_clk_freq_mhz line_length_pck frame_length_line ----------------------------------------------------------------------------------------------- = video timing vs6663cb 44/64 doc id026749 rev 2 figure 17. bayer pattern blue green green red blue green green red 3 2 1 0 1 3 2 0 5 4 blue green green red 5 4 7 6 1291 1290 1289 1288 971 973 972 970 1293 1292 975 974 1295 1294 blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red 976 active rows 1296 active columns doc id026749 rev 2 45/64 vs6663cb video timing 47 6.3 exposure and gain control vs6663cb does not contain any form of automatic exposure control. to produce a correctly exposed image the integration period and analog gain for the pixels must be calculated by an exposure control algorithm implemented externally. the parameters are then written to the vs6663cb through the cci interface. the exposure control parameters available on vs6663cb are: ? fine integration time ? coarse integration time ? analog gain ? digital gain the exposure control parameter registers are defined in section 4.2.6: integration time and gain registers [0x0200 to 0x02ff] on page 27 . integration time and analog ga in capability registers should be used to determine the exposure control parameter limits fo r a given video timing configuration. 6.3.1 gain model vs6663cb only supports the single global analog gain mode.the gain is monotonic to avoid instabilities in the exposure lo op vs6663cb has a 16-bit regi ster (0x0204 a nd 0x0205) to control analog gain. figure 18 shows how the analog gain bits are used for vs6663cb. figure 18. analog gain register format the following generic equation describes vs6663cb gain behavior specified by the analog gain description registers 0x008a to 0x0093: where: m 1 = -1 c 0 = 256 c 1 = 256 table 25 specifies the valid analog gain values for vs6663cb. table 25. analog gain control gain value (0x0204/0x0205) coarse gain code [a7:a4] coarse analog gain 0x0000 0000 0.00 db (x1.00) 0x0010 0001 0.6 db (x 1.07) 0x0020 0010 1.1 db (x1.14) 0x0030 0011 1.8 db (x1.23) a7 a6 a5 a4 a1 a0 a8 a9 a15 a14 a13 a12 a11 a10 coarse gain not used not used a3 a2 not used gain c0 m ( 1x ? ? c1 ) + = video timing vs6663cb 46/64 doc id026749 rev 2 6.3.2 digital gain to help compensate for the relatively coarse analogue gain steps, vs6663cb contains a digital multiplier to ?fill? in the missing step s. by mixing analogue and digital gain it is possible to implement 3% gain steps across the full 1x to 16x gain range the details of the digital gain implementation are listed below: ? four individual 16-bit digital channel gains - one per bayer channel ? digital_gain_greenr (0x020e and 0x020f) ? digital_gain_red (0x0210 and 0x0211) ? digital_gain_blue (0x0212 and 0x0213) ? digital_gain_greenb (0x0214 and 0x0215) ? the digital gain range for each channel is 0.0039 to 1.996 in steps of 0.0039 (1/256) ? digital_gain_min {0x1084:0x1085} = 0x0001 (0.0039) ? digital_gain_max {0x1086:0x1087} = 0x01ff (1.996) ? digital_gain_step {0x1088: 0x1089} = 0x0001 (0.0039) 6.3.3 integration and gain parameter retiming the modification of exposure parameter (coarse integration time or gain) register values does not take effect immediately. the exact time at which changes to certain pa rameters take effect is controlled both to ensure that each frame of image data produced has consistent settings and that changes in groups of related parameters can be synchronized. to eliminate the possibility of the sensor arra y seeing only part of the new exposure and gain setting, if the serial interface communications extends over a frame boundary, the internal retiming of exposure and gain data is disabled while writin g data to the serial interface register map. therefore if the 4 bytes of exposure and gain data is sent as an auto- 0x0040 0100 2.5 db (x1.33) 0x0050 0101 3.2 db (x1.45) 0x0060 0110 4.1 db (x1.60) 0x0070 0111 5.0 db (x1.78) 0x0080 1000 6.0 db(x2.00) 0x0090 1001 7.2 db (x2.29) 0x00a0 1010 8.5 db (x2.66) 0x00b0 1011 10.1 db (x3.20) 0x00c0 1100 12.0 db (x4.00) 0x00d0 1101 14.5 db (x5.33) 0x00e0 1110 18.1 db (x8.00) 0x00f0 1111 24.1 db (x16.00) table 25. analog gain control (continued) gain value (0x0204/0x0205) coarse gain code [a7:a4] coarse analog gain doc id026749 rev 2 47/64 vs6663cb video timing 47 increment cci sequence, it is not possible for the sensor to consume only part of the new exposure and gain data. however if it is not possible for the host to use auto-increment cci register accesses and only discrete register accesses are possible then the vs6663cb has a mechanism to temporarily suspend the automatic applicatio n of updated exposure register values. a group of parameter changes is marked by the host using a dedicated boolean control parameter, grouped_parameter_hold (register 0x0104). any changes made to ?retimed? parameters while the gr ouped_parameter_hold signal is in the ?hold? state will be considered part of the same group. only when the gr ouped_parameter_hold control signal is moved back to the default ?no-hold? state will the group of changes be executed by vs6663cb. electrical characteristics vs6663cb 48/64 doc id026749 rev 2 7 electrical characteristics all parameter values quoted in this outline produc t specification are design targets and will be confirmed by evaluation of initia l samples and device characterization. typical values quoted for nominal voltage, pr ocess and temperature. maximum values are quoted for worst case conditions (process, voltage and functional temperature) unless otherwise specified. 7.1 absolute maximum ratings caution: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating on ly and functional operati on of the device at these or any other conditions above those in dicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 26. absolute maximum ratings symbol parameter minimum maximum unit v digmax digital power supply -0.3 2.2 v v anamax analog power supply -0.3 3.2 v v ip(dig) digital input voltage (1) 1. digital input: extclk, xshutdown, scl, sda -0.3 v ana + 0.3 v t sto storage temperature -40 + 85 (2) 2. this is a maximum long term standard storage temper ature, see soldering profile for short term high temperature tolerance o c v esd electrostatic discharge model human body model (3) charge device model (4) 3. hbm tests are performed in compliance with jesd22-a114f mm test is performed in compliance with jesd22-a1 15a class b if hbm pass level is less than 1000v. 4. cdm esd tests are performed in compliance with jesd22-c101d -2 -500 2 500 kv v doc id026749 rev 2 49/64 vs6663cb electrical characteristics 55 7.2 operating conditions 7.3 power supply - vdig, vana 7.3.1 peak current the peak current consumption of the sensor module is def ined as any current pulse >=10 s. peak current is assumed to be <1.33 x maximum average current for the stated operating mode and worst case conditions. the dut y cycle of the peak to the low part of the current profile is 33% with a worst-case period of 500 s. table 27. operating conditions symbol parameter minimum typical maximum unit voltage vdig digital power supply 1.68 1.8 1.92 v vana analog power supply 2.6 2.8 2.9 v temperature t as temperature (storage (1) ) 1. camera has no permanent degradation. -40 - +85 c t af temperature (functional operating (2) ) 2. camera is electrically functional. -30 - +70 c t an temperature (normal operating (3) ) 3. camera produces ?acceptable? images. -25 - +55 c t ao temperature (optimal operating (4) ) (5) 4. camera produces optimal optical performance. 5. camera surface temperature. +5 - +40 c t at temperature (test (6) ) 6. 100% tested parameters are measured at this temperature. +21 - +25 c table 28. power supplies vdig, vana parameter digital analogue unit typical maximum typical maximum hardware standby 2 20 2 10 a streaming (1) 1. full resolution, 10-10data, 30 fps, csi-2 18 50 40 55 ma electrical characteristics vs6663cb 50/64 doc id026749 rev 2 7.4 system clock - extclk 7.5 power down control - xshutdown 7.6 cci interface - sda, scl 7.6.1 cci interface - dc specification table 29. system clock - extck symbol parameter minimum maximum unit f extclk clock frequency input 6.0 - 1% (1) 1. nominal frequencies are 6.0 to 27 mhz wi th a 1% centre frequency tolerance. 27 + 1% (1) mhz leakage current 4 (2) 2. with dc coupled square wave clock. 30 (3) 3. with dc vdig applied. a table 30. power down control - xshutdown symbol parameter minimum typical maximum unit v il low level input voltage 0 - 0.3 vdig v v ih high level input voltage 0.7 vdig - vana v table 31. cci interface - dc specification symbol parameter minimum maximum unit v il low level input voltage 0 0.3 * vdig v v ih high level input voltage 0.7 * vdig vdig v v ol low level output voltage (1) 1. v oh not valid for cci. 3ma drive strength 0 0.2 * vdig v i il low level input current - -10 a i ih high level input current - 10 a doc id026749 rev 2 51/64 vs6663cb electrical characteristics 55 7.6.2 cci interface - timing characteristics figure 19. cci ac characteristics all timings are measured from ei ther 0.3 vdig or 0.7 vdig. table 32. cci interface - timing characteristics symbol parameter minimum typical maximum unit t scl scl clock frequency 0 - 400 khz t low clock pulse width low 1.3 - - s t high clock pulse width high 0.6 - - s t sp pulse width of spikes which are suppressed by the input filter 0 - 50 ns t buf bus free time between transmissions 1.3 - - s t hd.sta start hold time 0.6 - - s t su.sta start set-up time 0.6 - - s t hd.dat data in hold time 0 - 0.9 s t su.dat data in set-up time 100 - - ns t r scl/sda rise time 20+0.1 cb (1) 1. cb = total capacitance of one bus line in pf - 300 ns t f scl/sda fall time 20+0.1 cb (1) - 300 ns t su.sto stop set-up time 0.6 - - s ci/o input/output capacitance (sda) - - 8 pf cin input capacitance (scl) - - 6 pf sda scl t hd.sta t r t high t f t su.dat t hd.dat t su.sta t su.sto ... ... t hd.sta t low t buf stop start stop start 0.7 vdig 0.3 vdig 0.3 vdig 0.7 vdig electrical characteristics vs6663cb 52/64 doc id026749 rev 2 7.7 ccp2 interface 7.7.1 ccp2 interface - dc specification 7.7.2 ccp2 interface - timing characteristics the parameters in table 34 are measured across a terminated 100 transmission line, in data/strobe mode. table 33. ccp2 interface - dc specification symbol parameter minimum typical maximum unit v od differential voltage swing (1) 1. measured over a 100 load 100 150 200 mv v cm common mode voltage (self biasing) 0.8 0.9 1.0 v r o output impedance 40 140 i dr drive current range (internally set by bias circuit) 0.5 1.5 2 ma psrr (2) 2. nominal value for the interference at v cm voltage through digital supply relative to the interference at digital supply over the 0-1 ghz operat ing range. psrr = 20*log10 (v dig interference (peak-to-peak) / v cm interference (peak-to-peak)) 0 - 100mhz - - 30 db 100 - 1000mhz - - 10 db table 34. ccp2 interface - timing characteristics symbol parameter min. max. unit f p average data frequency - 640 mbits/s t p average data period 1.56 - ns t jitter (1) 1. t pmax -t pmin data period jitter - 200 ps t stable both data and clock at the stable level 780 - ps t rise rise time of data+/data- ,clk+/clk- 300 400 ps t fall fall time of data+/data-, clk+/clk- 300 400 ps t skew (2) 2. t skew =t cmpskew + t chcskew total skew between signals - 225 ps t pwr power up/down time - 20 s doc id026749 rev 2 53/64 vs6663cb electrical characteristics 55 figure 20. sublvds ac timing 7.8 csi-2 interface 7.8.1 csi-2 interface - dc specification data+/ data- clk+/ clk- t cmpskew t stable t chcskew t pmin t pmax t fall t rise 80% 0.9v 20% 80% 0.9v 20% table 35. csi-2 interface - high speed mode - dc specification symbol parameter minimum typical maximum unit v cmtx hs transmit static common mode voltage 150 200 250 mv v od hs transmit differential voltage (1) 1. value when driving into load impedance anywhere in the z id range (80-125 ). 140 200 270 mv v ohhs hs output high voltage (1) 360 mv z os single ended output impedance 40 50 62.5 table 36. csi-2 interface - low power mode - dc specification symbol parameter minimum typical maximum unit v oh output high level 1.1 1.2 1.3 v v ol output low level -50 50 mv z olp output impedance of lp transmitter 110 electrical characteristics vs6663cb 54/64 doc id026749 rev 2 7.8.2 csi-2 interface - ac specification note: for further information on the d-phy please refer to the following specification document: mipi alliance st andard for d_ph y version 1.00. table 37. csi-2 interface - high speed mode - ac specification symbol parameter minimum typical maximum unit data rate 80 - 800 mbits/s t r and t f 20% - 80% rise time and fall time 150 0.3ui (1) 1. ui is equal to 1/(2*fh) where fh is the fundamental frequency of the transmission for a certain bit rate. for example, for 800 mbps, fh is 400 mhz. ps t skew data to clock skew -0.15ui - 0.15ui ps table 38. csi-2 interface - low power mode - ac specification symbol parameter minimum typical maximum unit t r and t f 15% - 85% rise time and fall time 25 ns doc id026749 rev 2 55/64 vs6663cb optical specification 55 8 optical specification 8.1 lens characteristics 8.2 user precaution as is common with many cmos image modules the camera should not be pointed at bright static objects for long periods of time as permanent damage to the sensor may occur. table 39. lens design characteristics parameter value 2-element plastic lens - f/number 2.8 effective focal length 2.31mm (paraxial) horizontal fov 50.7 nominal focusing distance 16 mm (referred to top of module) straylight no undesirable straylight artefacts to be present in image at contrast of: 1:10 5 out of scene 1:10 4 in scene spectral weighting: wavlength (nm) weight 656.28 151 587.56 318 546.07 312 486.13 157 435.84 49 404.66 13 lateral chromatic aberration from blue ( =435nm) to red ( =640nm) < |3.8 um| coating reflectance - all surfaces are coated. at least 50% of all surfaces must fulfil this specification. < 400 nm 400 - 670 nm >670 nm no limitation 1.0% absolute, 0.35% avg straight line with a slope of < 3% / 100nm maximum chief ray angle 29 on-chip image optimization vs6663cb 56/64 doc id026749 rev 2 9 on-chip image optimization 9.1 mapped couplet co rrection (bruce filter) the mapped couplet de fect correction filter is designed to intelligently correct the first defect in a couplet thereby changing a couplet into a single pixel defect. single pixel correction is achieved either by the median filter or by the host (coprocessor, mmp or baseband). the mapped couplet correction filter operates in both full resolution, and in binned mode. the mapped couplet correction filter requires exact coordinate information for each of the couplets to be repaired. the couplet coordinat es are stored in non-volatile-memory (nvm) during production test. the mapped couplet correction is controlled by register 0x0b05: 0 - disable 1 - enable 9.2 median filter this is a simple 1-d median filt er defect correction which replaces every pixel value by the median of itself, its predecessor and its successor (respecting the color pattern). the median filter operates in both full resolution, and in binned mode. it is suggested that this filter is only used for viewfinder images or other non stored images. (note that the median filter will not correct any defective pixels which occur in either the firs t two or the last two columns). the selection of the median filter is controlled using register (0x0b06) 0 - disable 1 - enable 9.3 lens shading correction the vs6663cb has an adaptive (four color temp erature) lens shading correction function which can be used to reduce the effect of roll off in the optical system. correction is carried out individually for all four color planes, each gain is calculated based on the distance from the image centre to the pixel in question using a two factor polynomial (r 2 and r 4 ). the lens shading filter operates in both full resolution, and in binned mode. the correction applied is 75%. in order to optimize the av algorithm, the coef ficients for each device are calculated under d65 (fluorescent philips graphica pro 965) lighting co nditions and programmed in the nvm memory at production test. (the coeffici ents from the nvm can be overwritten). settings for three other color temperatures (c ool white, u30, and horizon) are calculated from characterization data and these are stored in the nvm memory. the calculation of the color temperature is per formed by the sensor using the white balance gains. the white balance gains can either be calc ulated internally by the sensor or they can be calculated by the host a nd written back to the sensor. figure 21 provides an example of lens shading correction. doc id026749 rev 2 57/64 vs6663cb on-chip image optimization 57 figure 21. lens shading images original image corrected image mechanical vs6663cb 58/64 doc id026749 rev 2 10 mechanical figure 22. vs6663cb outline drawing - 1 of 3 - all dimensions in mm doc id026749 rev 2 59/64 vs6663cb mechanical 61 figure 23. vs6663cb outline drawing - 2 of 3 - all dimensions in mm mechanical vs6663cb 60/64 doc id026749 rev 2 figure 24. vs6663cb outline drawing - 3 of 3 - all dimensions in mm doc id026749 rev 2 61/64 vs6663cb application 61 11 application 11.1 schematic figure 25. mobile camera application vs6663cb 1.8v extclk data+ clk- gnd scl sda 1.8v external clock power down signal 100r 100r 4.7k xshutdown data- clk+ sublvds data sublvds clock cci control lines vdig 3.6v . 2.8v vana vcap notes: no connection should be made to vcap. cccp2 100r termination may be internal to sublvds receiv er. for csi-2, the receiver is mandated to have an internal termination which is dynamic ally switched in and out depending on whether the link is in high speed or low power mode. this trans ition occurs every line. 220nf . 220nf vcore charge pump 470nf ecopack ? vs6663cb 62/64 doc id026749 rev 2 12 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. doc id026749 rev 2 63/64 vs6663cb revision history 63 13 revision history table 40. document revision history date revision changes 13-oct-2014 1 initial release. 01-jul-2015 2 updated disclaimer vs6663cb 64/64 doc id026749 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
Price & Availability of VS6663CBQ05I
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |